FPGA Design Flow Lab #4 with Vivado 2013.4
The lab #4 in the FPGA Design Flow series found here comes with IP files for a FIFO generator but the version is older than what is found in the IP catalog. I got a very quick response on Xilinx's forum about a possible fix and there I detailed what I did. Simply, I issued a couple TCL commands in the console in Vivado which changed updated some file list for the FIFO generator. Though there were several warnings and ultimately a setup TNS of -18 ns, the ZYBO worked as expected once programmed.
My next step will be to start a blank project and I will attempt to add each source file and IP by hand and one by one so I can better understand the process of creating such a large project - though I suspect Lab 4 is actually quite small as far as real FPGA applications are concerned.
